This invention relates to improvements in integrated circuit processing, and more particularly, to minimizing damage to previously defined isolation structures and semiconductor surfaces during subsequent device processing steps.
Device isolation typically is achieved by utilizing local oxidation of silicon ("LOCOS") or shallow trench isolation ("STI") techniques. In the STI device isolation technique, isolation commonly is provided by forming a recess or trench between two active area mesas, upon which the electronic devices are located and filling the trench with an insulating material. Shallow trench isolation serves to provide higher packing density, improved isolation and greater planarity, by avoiding the topographical irregularities encountered when using conventional thick film oxide isolation (LOCOS). Typically, trench isolation technology includes a planarization process to remove oxide from the active area mesas and maintain oxide in the trenches.
Several techniques have been developed for planarization of wafer surfaces as part of trench isolation processing. These techniques are well known and have been disclosed in U.S. Pat. Nos. 5,492,858; 5,498,565; and 5,290,396.
FIG. 1 shows an active area mesa 16 formed on a semiconductor substrate 12 and isolated from surrounding semiconductor areas by insulating oxide 14 deposited in isolation trench 13 and insulating material 15 deposited in isolation trench 17. As shown in FIG. 1, surface 20 of substrate 12 is substantially planar with surfaces 18 and 19 of insulating materials 14 and 15, respectively. As previously explained, the process of planarization to remove insulating material from the surface of active area mesas and to maintain the material in the trenches is well known in the art.
Referring now to FIG. 2, a gate electrode 30 is formed on active area mesa 16 and is surrounded by spacer oxide 32. As known in the art, the surrounding semiconductor material is doped 26 as desired. Once spacer oxide 32 has been formed, the device may be processed to create a silicide layer 21 over the exposed semiconductor surfaces.
As shown in FIG. 2, a problem with the processing techniques of the prior art is that when defining device structures after planarization, particularly spacers 32 positioned adjacent to gate electrode 30, surface 20 of the semiconductor substrate may be damaged by the etchants used to form such structures. Damage to the semiconductor surface 20 may cause poor silicide formation 28 and result in decreased device performance. In addition to damage to the semiconductor surface, a portion of the insulating material 14 and 15 filling trenches 13 and 17, respectively, may also be lost during the etching process. After completion of device processing, the surfaces 18 and 19 of insulating oxide 14 and 15, respectively, are substantially spaced from surface 20. Surfaces 18 and 19 have been reduced from their previous positions by distance 22 and 23, respectively, and are below the level of doping 26 and silicide 21. Loss of insulating material 14 and 15 in isolating trenches 13 and 17, respectively, may result in junction leakage, causing poor device performance.
Therefore, there remains a need for a convenient and cost-effective process to protect the surface of the substrate and the insulating material in place in the isolation trenches during subsequent device processing steps.